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1/14 august 2001 n high speed: f max = 79 mhz (typ.) at v cc = 6v n low power dissipation: i cc = 4 m a(max.) at t a =25c n high noise immunity: v nih = v nil = 28 % v cc (min.) n symmetrical output impedance: |i oh | = i ol = 6ma (min) n balanced propagation delays: t plh @ t phl n wide operating voltage range: v cc (opr) = 2v to 6v n pin and function compatible with 74 series 652 description the m74hc652 is an advanced high-speed cmos octal bus transceiver and register (3-state) fabricated with silicon gate c 2 mos technology. this device consists of bus transceiver circuits, d-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal storage registers. enable gab and gba are provided to control the transceiver functions. select ab (sab) and select ba (sba) control pins are provided to select whether real-time or stored data is transferred. a low input level selects real-time data, and a high selects stored data. data on the a or b bus, or both, can be stored in the internal d flip-flops by low-to-high transition at the appropriate clock pins (clock ab or clock ba) regardless of the select or enable control pins. when select ab and select ba are in the real time transfer mode, it is also possible to store data without using the internal d type flip-flops by simultaneously enabling gab and gba . in this configuration each output reinforces its input. thus, when all other data sources to the two sets of bus lines are at high impedance, each set of bus lines will remain at its last state. all inputs are equipped with protection circuits against static discharge and transient excess voltage. m74hc652 octal bus transceiver/register with 3 state outputs pin connection and iec logic symbols order codes package tube t & r dip M74HC652B1R sop m74hc652m1r m74hc652rm13tr tssop m74hc652ttr tssop dip sop
m74hc652 2/14 input and output equivalent circuit pin description truth table pin no symbol name and function 1 cab a to b clock input (low to high, edge-triggered) 2 sab select a to b source input 3 gab direction control input 4, 5, 6, 7, 8, 9, 10, 11 a1 to a8 a data inputs/outputs 20, 19, 18, 17, 16, 15, 14, 13 b1 to b8 b data inputs/outputs 21 gba output enable input (active low) 22 sba select b to a source input 23 cba b to a clock input (low to high, edge triggered) 12 gnd ground (0v) 24 v cc positive supply voltage gab gba cab cba sab sba a b function lh inputs inputs both the a bus and the b bus are inputs x x x x z z the output functions of the a and b bus are disabled x x inputs inputs both the a and b bus are used for inputs to the internal flip-flops. data at the bus will be stored on low to high transition of the clock inputs. ll outputs inputs the a bus are outputs and the b bus are inputs x* x x l ll the data at the b bus are displayed at the a bus hh x* x l l l the data at the b bus are displayed at the a bus. the data of the b bus are stored to internal flip-flop on low to high transition of the clock pulse hh x*xxh qn x the data stored to the internal flip-flop are displayed at the a bus. x* x h l l the data at the b bus are stored to the internal flip-flop on low to high transition of the clock pulse. the states of the internal flip-flops output directly to the a bus. hh hh inputs outputs the a bus are inputs and the b bus are outputs. xx*l x ll the data at the a bus are displayed at the b bus hh x* l x l l the data at the a bus are displayed at the b bus. the data of the a bus are stored to the internal flip-flop on low to high transition of the clock pulse. hh xx*h x x qn the data stored to the internal flip-flops are displayed at the b bus x* h x l l the data at the a bus are stored to the internal flip-flop on low to high transition of the clock pulse. the states of the internal flip-flops output directly to the b bus. x* h x h h
m74hc652 3/14 x : dont care z : high impedance qn : the data stored to the internal flip-flops by most recent low to high transition of the clock inputs * : the data at the a and b bus will be stored to the internal flip-flops on every low to high transition of the clock inputs. logic diagram timing chart hl outputs outputs x x h h qn qn the data stored to the internal flip-flops are displayed at the a and b bus respectively. h h qn qn the output at the a bus are displayed at the b bus, the output at the b bus are displayed at the a bus respec- tively gab gba cab cba sab sba a b function
m74hc652 4/14 absolute maximum ratings absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditi ons is not implied (*) 500mw at 65 c; derate to 300mw by 10mw/ c from 65 c to 85 c recommended operating conditions symbol parameter value unit v cc supply voltage -0.5 to +7 v v i dc input voltage -0.5 to v cc + 0.5 v v o dc output voltage -0.5 to v cc + 0.5 v i ik dc input diode current 20 ma i ok dc output diode current 20 ma i o dc output current 35 ma i cc or i gnd dc v cc or ground current 70 ma p d power dissipation 500(*) mw t stg storage temperature -65 to +150 c t l lead temperature (10 sec) 300 c symbol parameter value unit v cc supply voltage 2 to 6 v v i input voltage 0 to v cc v v o output voltage 0 to v cc v t op operating temperature -55 to 125 c t r , t f input rise and fall time v cc = 2.0v 0 to 1000 ns v cc = 4.5v 0 to 500 ns v cc = 6.0v 0 to 400 ns
m74hc652 5/14 dc specifications symbol parameter test condition value unit v cc (v) t a = 25c -40 to 85c -55 to 125c min. typ. max. min. max. min. max. v ih high level input voltage 2.0 1.5 1.5 1.5 v 4.5 3.15 3.15 3.15 6.0 4.2 4.2 4.2 v il low level input voltage 2.0 0.5 0.5 0.5 v 4.5 1.35 1.35 1.35 6.0 1.8 1.8 1.8 v oh high level output voltage 2.0 i o =-20 m a 1.9 2.0 1.9 1.9 v 4.5 i o =-20 m a 4.4 4.5 4.4 4.4 6.0 i o =-20 m a 5.9 6.0 5.9 5.9 4.5 i o =-6.0 ma 4.18 4.31 4.13 4.10 6.0 i o =-7.8 ma 5.68 5.8 5.63 5.60 v ol low level output voltage 2.0 i o =20 m a 0.0 0.1 0.1 0.1 v 4.5 i o =20 m a 0.0 0.1 0.1 0.1 6.0 i o =20 m a 0.0 0.1 0.1 0.1 4.5 i o =6.0 ma 0.17 0.26 0.37 0.40 6.0 i o =7.8 ma 0.18 0.26 0.37 0.40 i i input leakage current 6.0 v i = v cc or gnd 0.1 1 1 m a i oz high impedance output leakage current 6.0 v i = v ih or v il v o = v cc or gnd 0.5 5 5 m a i cc quiescent supply current 6.0 v i = v cc or gnd 44080 m a
m74hc652 6/14 ac electrical characteristics (c l = 50 pf, input t r = t f = 6ns) symbol parameter test condition value unit v cc (v) c l (pf) t a = 25c -40 to 85c -55 to 125c min. typ. max. min. max. min. max. t tlh t thl output transition time 2.0 50 25 60 75 90 ns 4.5 7121522 6.0 6101319 t plh t phl propagation delay time (bus - bus) 2.0 50 74 150 190 210 ns 4.5 21 30 38 50 6.0 18 26 32 40 2.0 150 91 190 240 255 ns 4.5 26 38 48 60 6.0 22 32 41 55 t plh t phl propagation delay time (clock - bus) 2.0 50 98 210 265 280 ns 4.5 28 42 53 68 6.0 24 36 45 57 2.0 150 116 250 315 330 ns 4.5 33 50 63 80 6.0 28 43 54 70 t plh t phl propagation delay time (select - bus) 2.0 50 81 170 215 230 ns 4.5 23 34 43 60 6.0 20 29 37 50 2.0 150 98 210 265 280 ns 4.5 28 42 53 60 6.0 24 36 45 58 t pzl t pzh high impedance output enable time 2.0 50 r l = 1 k w 74 175 220 240 ns 4.5 21 35 44 56 6.0 18 30 37 50 2.0 150 r l = 1 k w 91 215 270 290 ns 4.5 26 43 54 67 6.0 22 37 46 60 t plz t phz high impedance output disable time 2.0 50 r l = 1 k w 50 175 220 230 ns 4.5 21 35 44 57 6.0 18 30 37 46 f max maximum clock frequency 2.0 50 6 19 4.8 4.0 mhz 4.5 30 67 24 21 6.0 35 79 28 25 t w(h) t w(l) minimum pulse width 2.0 50 30 75 95 110 ns 4.5 7151925 6.0 6131620 t s minimum set-up time 2.0 50 16 50 65 75 ns 4.5 4101315 6.0 3 9 11 13 t h minimum hold time 2.0 50 555 ns 4.5 5 5 5 6.0 5 5 5
m74hc652 7/14 capacitive characteristics 1) c pd is defined as the value of the ics internal equivalent capacitance which is calculated from the operating current consumption without load. (refer to test circuit). average operating current can be obtained by the following equation. i cc(opr) = c pd x v cc x f in + i cc /8 (per channel) test circuit c l = 50pf/150pf or equivalent (includes jig and probe capacitance) r 1 = 1k w or equivalent r t = z out of pulse generator (typically 50 w ) symbol parameter test condition value unit v cc (v) t a = 25c -40 to 85c -55 to 125c min. typ. max. min. max. min. max. c in input capacitance 5101010pf c pd power dissipation capacitance (note 1) 38 pf test switch t plh , t phl open t pzl , t plz v cc t pzh , t phz gnd
m74hc652 8/14 waveform 1 : propagation delay time (f=1mhz; 50% duty cycle) waveform 2 : minimum pulse width, propagation delay (f=1mhz; 50% duty cycle)
m74hc652 9/14 waveform 3 : minimum setup and hold time (f=1mhz; 50% duty cycle) waveform 4 : output enable and disable time (f=1mhz; 50% duty cycle)
m74hc652 10/14 waveform 5 : output enable and disable time (f=1mhz; 50% duty cycle)
m74hc652 11/14 dim. mm. inch min. typ max. min. typ. max. a1 0.63 0.025 b 0.45 0.018 b1 0.23 0.31 0.009 0.012 b2 1.27 0.500 d 32.2 1.268 e 15.2 16.68 0.598 0.657 e 2.54 0.100 e3 27.94 1.100 f 14.1 0.555 i 4.445 0.175 l 3.3 0.130 plastic dip-24 (0.25) mechanical data p043a
m74hc652 12/14 dim. mm. inch min. typ max. min. typ. max. a 2.65 0.104 a1 0.1 0.2 0.004 0.008 a2 2.45 0.096 b 0.35 0.49 0.014 0.019 b1 0.23 0.32 0.009 0.012 c 0.5 0.020 c1 45 (typ.) d 15.20 15.60 0.598 0.614 e 10.00 10.65 0.393 0.419 e 1.27 0.050 e3 13.97 0.550 f 7.40 7.60 0.291 0.300 l 0.50 1.27 0.020 0.050 s8 (max.) so-24 mechanical data po13t f c l e a1 b1 a e d e3 b 24 13 112 c1 s a2
m74hc652 13/14 dim. mm. inch min. typ max. min. typ. max. a 1.1 0.043 a1 0.05 0.15 0.002 0.006 a2 0.9 0.035 b 0.19 0.30 0.0075 0.0118 c 0.09 0.20 0.0035 0.0079 d 7.7 7.9 0.303 0.311 e 6.25 6.5 0.246 0.256 e1 4.3 4.5 0.169 0.177 e 0.65 bsc 0.0256 bsc k0 80 8 l 0.50 0.70 0.020 0.028 tssop24 mechanical data c e b a2 a e1 d 1 pin 1 identification a1 l k e 7047476a
m74hc652 14/14 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result f rom its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specificati ons mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. ? the st logo is a registered trademark of stmicroelectronics ? 2001 stmicroelectronics - printed in italy - all rights reserved stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco singapore - spain - sweden - switzerland - united kingdom ? http://www.st.com

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